2011/11/21

module top;
reg [1:0] A, B;
reg Cin;
wire[1:0] Sum;
adder2 M2(Cout, Sum, A, B, Cin);
initial 
begin 
A=2'd1; 
B=2'd1; 
Cin=1'd1; 
end
endmodule
module adder2(Cout, Sum, A, B, Cin);
output Cout;
module top; 
system_clock #400 clock1(Cin); 
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder 01(Cout,Sum,Cin,A,B);
endmodule 
module adder(Cout,Sum,Cin,A,B);
input A,B,Cin;
output Cout,sum;
and I1(sel_01,A,B);
xor I2(sel_02,A,B);
and I3(sel_03,sel_02,Cin);
or I4(Cout,sel_01,sel_03);
xor I5(Sum,sel_02,Cin);
endmodule


module system_clock(clk); 
parameter PERIOD=100; 
output clk; 
reg clk; 
initial 
clk=0; 
always 
begin
#(PERIOD/2)clk=~clk; 
end 
always@(posedge clk)
if($time>1000)
$stop; 
endmodule 

2011/11/07

module top;
system_clock #200 clock2(A);
system_clock #100 clock3(B);
system_clock #400 clock1(Cin);
adder  mml(Cout,Sum,Cin,A,B);
endmodule

module adder(Cout,Sum,Cin,A,B);
input A,B,Cin;
output Cout,Sum;
and(sel_01,A,B);
xor(sel_02,A,B);
and(sel_03,sel_02,Cin);
or(Cout,sel_01,sel_03);
xor(Sum,sel_02,Cin);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2011年10月3日 作業

module top;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);

mux ml(OUT,A,B,SEL);
endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule



2011/10/03
作業!